Deploying hardware like software: our open Zynq pipeline
A REST endpoint on the board, one POST with a bitstream, and the FPGA next to the processor runs the design. This is how we bring up Zynq SoCs.
A Zynq-7020 is half a computer and half an FPGA on one die. The ARM side runs Linux, the FPGA side can be reconfigured at runtime in well under a second. Most teams still program it like a microcontroller from the nineties: a cable, a vendor tool, a ritual.
We take a different route and document it publicly on an ALINX AX7020. The goal is a REST API on the board that accepts a bitstream, as the last step of a hardware CI pipeline. Five stages lead there: mainline U-Boot over JTAG without FSBL and without a serial cable, a self-built Yocto Linux in QSPI flash that fetches its own updates, then FPGA manager, API and pipeline.
Stages one to three are done and written up, including the uncomfortable parts, such as a JTAG probe that detects the board without power. This is exactly the work we offer as a service: software bring-up for Zynq SoCs with U-Boot, device tree and Yocto with SBOM, independent of the vendor workflow.
The concept and each stage are on the blog. Anyone bringing up their own Zynq design will save a few weeks with this series.